Power distribution system for integrated circuits

ABSTRACT

A power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over.

RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 11/757,265, filed Jun. 1, 2007, which claims benefit under 35U.S.C. §119(e) of U.S. Provisional Application No. 60/804,089, filedJun. 6, 2006; U.S. Provisional Application No. 60/887,148, filed Jan.29, 2007; and U.S. Provisional Application No. 60/887,149, filed Jan.30, 2007.

TECHNICAL FIELD

The present invention relates to power distribution for integratedcircuits (ICs). More specifically, the present invention relates topower distribution for ICs connected to printed circuit boards (PCBs).

2. Background Information

In recent years, high speed operation of electronic circuit devices hasbeen demanded and research thereon has been carried out. Electroniccircuit devices that can operate at high speed would enable the time ofprocessing, which formerly took a long time, to be shorteneddrastically, would allow processing formerly considered impossible to beperformed, and would make it possible to execute a large number of taskswith one device instead of multiple devices, thus reducing processingcosts and contributing to development of services, facilities,functions, etc.

The supply voltage of an electronic circuit should not substantiallychange over time. Even though the electronic circuit's consumption ofcurrent does substantially fluctuate over short periods of time, if thesupply voltage substantially changes, the electronic circuit, includingICs, will malfunction. The basic power distribution task can be simplystated as: the power distribution must support load current across theload signal spectrum while maintaining the load voltage withinacceptable limits for reliable operation. If the supply voltagesubstantially changes, the electronic circuit, including ICs, can beunable to maintain normal operation, and the output voltage of theelectronic circuit can change, making it impossible to provide normaloutput signals. The change of output voltage can be interpreted as noisein the output signals. If the noise is large, the electronic circuit caneven malfunction.

For this reason, the power distribution system and the power wiringsystem are designed to have a low impedance. These systems are designednot only to have a low direct current (DC) resistance, but also to havea low impedance with respect to alternating current (AC) or highfrequency signals. If the impedance of the power distribution system andpower wiring system is low, even when the consumption current of thecircuit fluctuates, the fluctuation of the supply voltage is small andthe noise of the circuit is also small. The electronic circuit canoperate normally, and therefore, the device, including the electroniccircuit, operates normally.

Assuming that the impedance of the power distribution system and powerwiring system is Z and that a fluctuation of the circuit's consumptioncurrent is ΔI, a supply voltage fluctuation ΔV is represented by.

ΔV=ZΔI

Because a part of this becomes a noise signal, a noise voltage V_(n) isrepresented by, where k is a coefficient of 0 to 1:

V _(noise) =k×ΔV=k×Z×ΔI.

As can be seen from these expressions, if the impedance Z of the powerdistribution system and power wiring system is small, the supply voltagefluctuation ΔV and noise voltage V_(noise) are also small. Therefore,the electronic circuit, including any ICs, can operate normally.

Most current ICs make little attempt to control damping between thereactive elements in the IC, IC die, and in-package capacitance and thelargely inductive path between the IC internal power connections and theremainder of the application PCB level power delivery system. Further,the total inductance is a function of individual PCB design. This leavesthe cut-off frequency and the damping factor of the inherent IC packagelow-pass filter dependent on the application PCB design. If the PCBpower delivery system impedance is inductive, and/or if the PCB powerdistribution system (sometimes referred to as power network wiring)resistive impedance is too low, then undesirable resonance occurs withinthe IC package.

Various techniques have been used to lessen the impedance of the powerdistribution system and the power wiring system (which will behereinafter referred to simply as the power distribution system). Thesevarious techniques include:

1. finely spaced filter zeroes;

2. high loss dielectric;

3. high skin loss interconnect;

4. using high equivalent series resistance (ESR) capacitors;

5. using bypass capacitors;

6. increasing cross-section of power wires; and

7. distributed RC networks to damp the inherent poles.

The use of finely spaced filter zeroes is discussed by Larry Smith andis essentially an implementation of techniques described byBaudendistel, in “Power Bus Decoupling on Multilayer Printed CircuitBoards”, TR94-8-023, University of Missouri-Rolla ElectromagneticCompatibility Laboratory, May 1994, which is discussed below.

High loss dielectric is an insulator material used in power wiring thatabsorbs energy by way of the work done by a changing electric fieldturning molecular dipoles in the high loss dielectric material. Itappears as a frequency dependent resistance across the power rails,absorbing more energy at high frequency than at low frequencies. This isdiscussed, for example, in Novak '258 (U.S. Pat. No. 6,104,258) andNovak '774 (U.S. Pat. No. 6,727,774), discussed below.

High skin loss increases the power wiring impedance. On the one hand,this decreases the power distribution system's ability to delivercurrent, locally increasing the noise amplitude. On the other hand,because high skin loss is dissipative, it suppresses resonance in thepower wiring network and suppresses noise propagation.

High ESR capacitors flatten the impedance of a given capacitor andprovide dissipative shunt loss. For a signal spectrum with a flatmaximum amplitude, a network with a constant impedance ideally resultsin peak to peak noise one half of a network with the same high frequencyimpedance, but where the impedance at middle or low signal frequenciesis much lower, for example, at a ratio of 5:1, than at high frequencies.The relationship of lower impedance at low frequency(s) versus higherfrequency gives rise to a noise high-pass function. The application of apulse to a high pass filter where the pulse is substantially longer thanthe filter's time constant affects proximate differentiation of thenoise pulse. The noise consists of an impulse at the leading edge, andan impulse at the trailing edge, each of similar magnitude set by thehigh frequency shunt impedance. For a pulse significantly longer thanthe filter time constant, the leading impulse recovers close to zeroprior to the opposing impulse. When the impedance is constant, theresponse is simply that of a scalar, deflecting from zero for theduration of the pulse and recovering to zero at the end of the pulse.When the ESR of a capacitor is high, the ESR dominates capacitorimpedance over a broad frequency range and makes it easier to avoid thehigh pass noise filter characteristic common to filters made with lowESR capacitors.

A technique of using bypass capacitors and a technique of increasing across-section of the power wiring are widely used prior art techniques.

A bypass capacitor is a capacitor of substantial capacity connectedbetween two power wires. Power is always supplied on two or more wires,such as 5 V (volts) and ground; the bypass capacitor is connectedbetween the two wires. If three or more wires, such as 5 V, 3 V, andground, are used, the bypass capacitor is connected between two wiressuch as the 5 V wire and ground or the 3 V wire and ground. The bypasscapacitor is often connected between ground and other wires, but it isnot necessary to provide for all combinations of wires.

A theoretical capacitor, which by its nature has an impedance thatdecreases as frequency increases, has an effect of reducing theimpedance of the power distribution system in alternating current orhigh frequency signal situations. A theoretical inductor, which by itsnature has an impedance that increases as frequency increases, has aneffect of increasing the impedance of the power distribution system inalternating current or high frequency signal situations. Therefore, atequal cost and complexity, it is desirable to construct the powerdistribution system so as to not exhibit any significant inductivecharacteristic within the load current spectrum.

Normally, in a power distribution system, a voltage regulator unit(alternatively, a voltage regulator module (VRM)) and an electroniccircuit, including any ICs, are connected by electric wiring. A typicalarrangement of the power distribution system is shown in FIG. 11. An ICpackage 10 and a voltage regulator module 13 are mounted on a PCB 12.The IC package 10 includes a die 11.

A power distribution system impedance for an alternating current or highfrequency situation viewed from the electronic circuit increases becauseof the inductance of the wiring connecting the electronic circuit andthe power distribution system. Then, when a bypass capacitor isconnected near the electronic circuit, the power distribution systemimpedance viewed from the electronic circuit decreases. Particularly,for high speed electronic circuits, the high frequency characteristic ofthe power distribution system impedance must be low.

A bypass capacitor typically is located very near the electronic circuitfor decreasing the inductance between the electronic circuit and thebypass capacitor. When a plurality of electronic circuits exists, abypass capacitor typically is provided sufficiently close to eachelectronic circuit or for each group of a small number of electroniccircuits. This power distribution system impedance reduction techniqueusing bypass capacitors reduces the power distribution system impedancefor alternating current or high frequency signals as viewed from theelectronic circuit, although the impedance of the wiring connecting theelectronic circuit and the power distribution system remains unchangedand in many cases dominates the power distribution impedance.

Another power distribution system impedance reduction technique is toincrease a cross-section of the power distribution wiring in order toreduce power distribution wiring inductance and power distributionsystem impedance. To effectively carry out this technique, the powerdistribution wiring is often made wide, specifically, in the shape of aplane. For example, with printed circuit boards and other similardevices, a multilayer structure is adopted to provide a powerdistribution layer, and the power distribution wiring in this powerdistribution layer is made flat. Often, through holes are required forconnecting parts and wires, and the plane of the power distributionlayer is perforated like a mesh. Generally, because at least one of thepower distribution wires is ground, ground is also contained in thepower distribution wiring.

If the power distribution wiring is formed like a plane, the inductanceof the power distribution wiring in the circuit board and that of thepower distribution wiring between the bypass capacitor and electroniccircuit can be lowered drastically, enabling reduction of the powerdistribution system impedance for alternating current or high frequencysignals.

Another technique is to reduce the spacing between the powerdistribution wires (vertical separation in the case of planar wires) toreduce the inductance, which is similar to the technique of reducing theinductance by increasing the width of the power distribution wires.

The two power distribution system impedance reduction techniques,increasing the cross-section of the power wiring and reducing spacingbetween power distribution wiring, described above can be used incombination and often are used in combination. These techniques arecompatible with each other for reducing the power distribution systemimpedance.

Prior art techniques also include gross application of distributed R-L-Cnetworks that attempt to realize a net flat to low-pass noise transferfunction for power distribution systems that rely upon power planes.

Baudendistel (“Power Bus Decoupling on Multilayer Printed CircuitBoards,” TR94-8-023, University of Missouri-Rolla ElectromagneticCompatibility Laboratory, May 1994) discloses how to determine values ofdamping elements used to suppress power distribution system resonances,which cause high impedances within the power distribution bandwidth. Forlow frequencies where the impedance of the power plane cavities(L_(PLN)) is low and where the resistance of the plane (R_(PLN)) is alsolow, Baudendistel uses a simple one-dimensional approximation toestimate power distribution system behavior up to the resonance betweenthe bypass capacitor network and any power plane cavity.

Baudendistel's model consists of n parallel RLC branches as shown inFIG. 1. The relationship between the frequency and the impedance, Z,based upon this model is shown in FIG. 2. Each branch represents theparallel aggregate for a particular capacitor value. Each parameter,R_(VALi) L_(VALi) and C_(VALi), where I=1, . . . , n, represents theparallel equivalent of the respective value from each device. Forexample, given ten instances of 1 μF, 2 mΩ, 1 nH capacitors, the branchis represented by a 10 μF, 0.2 mΩ, 0.1 nH capacitor. The parallel platecapacitance of the power/ground wiring cavity is represented by a singlecapacitor, C_(PLN).

As seen in FIG. 3, Baudendistel reduces the peaks of the resonances byincreasing the magnitude of the resistance, Rx, with respect to thecorresponding inductance, Lx, where x is one of 1, . . . , n, so as toflatten the impedance transitions from the region in which the impedanceis dominated by the (n−1)^(th) inductor (the region that has an upwardslope approximated by jωL_(VALn-1)) to the region in which the impedanceis dominated by the n^(th) capacitor (the region that has a downwardslope approximated by 1/(jωC_(VALn))).

Baudendistal enumerates impedance equations for each branch and branchesin parallel. Except for the voltage regulator module, VRM, each branchexhibits a series resonant frequency, SRF. The VRM interacts primarilywith the branch that has the lowest SRF. At a sufficiently highfrequency, the inductive reactance jωL_(VRM) crosses R_(VRM), as seen onthe left side of FIG. 2. The impedance increases to the point wherejωL_(VRM)=1/jωC_(VAL1). Impedance then decreases until the zero where1/jωC_(VAL1)=jωL^(VAL1). The residual impedance at this zero isR_(VAL1). This is best understood by examining the following equationfor a given component:

Z _(equivalent) =R _(equivalent) +j(ωL _(equivalent)−1/ωC _(equivalent))

where Z_(equivalent) is the total equivalent impedance, R_(equivalent)is the equivalent resistance, L_(equivalent) is the equivalentinductance, C_(equivalent) is the equivalent capacitance, j is theimaginary number −1, and ω is the angular frequency in radians/second.As the frequency increases, jωL_(VAL1) quickly dominates, increasing theimpedance until the pole where jωL_(VAL1) crosses 1/jωC_(VAL2). Theimpedance modulates between zeroes and poles until the last pole atw=(L_(VALN)*C_(PLN))^(−0.5). The extent of impedance modulation dependson the relative quality factor at each zero and pole. The Q factor isthe ratio of the inductive reactance to the resistive impedance at therespective pole or zero. A lower Q factor results in less modulation,while a higher Q results in more modulation.

Baudendistal teaches suppression of the impedance peaks at the poles byone or more of the following techniques:

1. Decreasing the series inductance in a given branch or branches;

2. Increasing the series resistance in a given branch or branches; and

3. Increasing the capacitance in the higher frequency branch of a twobranch pair forming a pole, thus decreasing the frequency of the poleand jωL.

Lee et al. “Modeling and Analysis of Multichip Module Power SupplyPlanes,” IEEE Transaction on Components, Packaging and ManufacturingTechnology; Part B, Vol. 18, No 4, November 1995) refines the model ofBaudendistel by including the distributed effects of the power planecavities and by including the modal resonances, which are shown on theright hand side of FIG. 7, of the power plane cavities that result fromwave reflections at the cavity's boundaries. Specifically, Lee et al.discretizes the power planar cavity into an array of cells as seen inFIGS. 4, 5A-5D, and 6. The cell size is selected to be small compared tothe wavelength of the highest frequency of interest (e.g., 1/10^(th)wavelength of the highest frequency of interest or less) in the powerdistribution system. The cell is then represented either by anequivalent network of resistances, inductances, and capacitance as shownin FIGS. 5A-5D or by a square formed by four intersecting transmissionlines as shown in FIG. 6. Lee et al. further suppresses resonances byusing thin film materials that exhibit high capacitance and significantdistributed damping resistance, i.e., the resistance is distributed overthe spatial extent of the structure, as opposed to contained in alocalized region or discrete component.

Lee et al. first offers a model using R-L-C equivalents as shown in FIG.4. Lee et al. derives the inductance and capacitance values from theTelegrapher's Equations. Lee et al. defines three types of cells:interior, edge, and corner as seen in FIGS. 5A-5C.

For computational economy, Lee et al. offers a similar model based onmeshed transmission lines, as seen in FIG. 6.

Lee et al. utilizes transmission lines with an impedance ofZ_(INT)=√2*(L/C)^(0.5) inside the outer perimeter and transmission lineswith twice the Z_(INT), 2*√2*(L/C)^(0.5), around the outer perimeter.

At each interior junction, four lines propagate energy away from anyinstant source, resulting in an impedance of:

Z _(INT) _(—) _(JUNC)=(L/(8C))^(0.5) =H/X*(μ/(8ε))^(0.5).

At each external junction along an edge, the impedance is twice Z_(INT)_(—) _(JUNC):

Z _(EDG) _(—) _(JUNC)=2*Z _(INT) _(—) _(JUNC) =H/X*(μ/(2ε))^(0.5).

At each corner, the impedance is four times

Z_(CORNER)=4*Z _(INT) _(—) _(JUNC) =H/X*(2μ/ε)^(0.5).

These impedance values account for neither the loading caused by anyattached components nor the density variation caused by arrays of viaanti-pads, where anti-pads are perforations in the planes that provideseparation between the planes and conductor vias passing through, butnot connecting to, those planes.

Novak '258 (U.S. Pat. No. 6,104,258) teaches the addition of terminationnetworks along the perimeter of the cavity defined by the power wiringas a means to match the cavity's interior impedance at the edges so asto suppress the reflections and the resulting modal resonances in thepower wiring. Novak '258 teaches that to be effective, the mountedinductance of termination networks should be no more than 0.2 times theinductance of the region terminated.

Novak '258 discloses that the impedance depends on the geometry,permittivity, and permeability of the cavity alone. However, Novak '258does not account for the loading of the bypass and/or the activecomponents. In situations where the board level components substantiallyload the power cavity impedance or where the frequency is above thefirst modal resonance, the method taught by Novak '258 does not matchthe impedance and will allow substantial reflections.

Instead of the edge termination method taught by Novak '258, Yamamura etal. (U.S. Pat. No. 5,844,762) discloses a distribution of dampingelements 14 connected to transmission lines 15 substantially throughoutthe entire printed circuit assembly, as seen in FIGS. 8A and 8B.Yamamura et al. teaches that an even distribution is ideal.

It can be seen that Yamamura et al. can successfully address branchresonances taught by Baudendistel by merely following Baudendistal'steachings. It can be seen from Lee et al. that Yamamura et al. fails toaddress the root cause of modal resonances of the power/groundcavity(s): mismatched impedance at the edge boundaries. It can also beseen from Lee et al. that Yamamura et al. can successfully suppressmodal resonances in cases where the damping element impedance is bothsubstantially less than the characteristic impedance of the meshedtransmission lines and substantially resistive.

By contrast, Novak '258 and Novak '774 (U.S. Pat. No. 6,727,774) teachthat to suppress modal resonances, it is sufficient to add terminationnetworks substantially along the PCB boundary so as to match theperipheral impedance to the internal impedance of the plane cavity(s).In doing so, Novak '258 and Novak '774 suppress modal resonances withfar fewer components and expense than Yamamura et al. However, similarto Yamamura et al., Novak '258 and '774 both rely upon achieving a lowinductance in the damping elements compared to the plane cavity itself.Novak recites a target inductance in the termination networks of no morethan:

0.2*μ₀*μ_(R) *H

where μ₀ is the permeability of free space (approximately 31.9×10⁻⁹webers/ampere), μ_(R) is the relative permeability of the conductors(generally 1.0 webers/ampere or very close to 1.0 webers/ampere), and His the dielectric thickness within the plane cavity.

For example, given a cavity with a dielectric thickness of 0.001″, thetarget inductance would need to be <0.2 *31.9×10⁻⁹ webers/ampere*1webers/ampere*0.001 in =6.4 pH. If implemented using common capacitorsand if using the planes near the surface of the PCB, the mountedinductance of each capacitor could be about 1 nH, requiring about 160components. For the case of a power/ground cavity further from thesurface of the PCB, such as occurs in a number of complex assemblies,the mounted inductance of each capacitor can be twice as high, requiringdouble the number of capacitors.

As can be understood from Lee et al., well within an unloaded cavityperimeter, the impedance closely follows:

Z _(INT) _(—) _(JUNC) =H/X*(μ/(8ε))^(0.5).

Well away from the corners along the edges, the impedance closelyfollows:

Z_(EDG) _(—) _(JUNC) =H/X*(μ/(2ε))^(0.5)=2*Z _(INT) _(—) _(JUNC).

At each corner, the impedance closely follows:

Z _(CORNER) =H/X*(2μ/ε)^(0.5)=4*Z _(INT) _(—) _(JUNC).

As seen in FIG. 9, a dissipative element 17 with resistive impedance ofZ_(EDG) _(—) _(TERM)=Z_(EDG) _(—) _(JUNC) (where Z_(EDG) _(—) _(TERM) isthe impedance of the dissipative element located on the boundary edge,but not at the corner) is connected to the edge of the transmissionlines 18 and nominally reduces the impedance along the boundary edge byhalf, and thereby matches Z_(INT) _(—) _(JUNC). In the case of anunloaded, rectangular cavity, this leaves reflections only from theimpedance mismatch in the corners where cavity impedance is twice ashigh as in the center of a given edge.

In order to compensate for the corners, as seen in FIG. 9, thedissipative element 16 is connected to the corner of the transmissionlines 18 and must assume a value that is not only substantively lowerthan the characteristic impedance of the corner itself, but also lowerthan the impedance in the center of each adjoining edge. Thus, theimpedance of the dissipative element 16 located at the corner(Z_(CORNER) _(—) _(TERM)) should be:

Z _(CORNER) _(—)_(TERM)=1/((X/H*(μ/8ε))^(0.5))−(X/H*(2μ/ε)^(0.5)))=4/3*Z _(INT) _(—)_(JUNC)=1/3*H/X*(2μ/ε)^(0.5).

This formula is derived by solving for the parallel impedance in thecorner required to maintain a uniform impedance along the boundary.

When uniformly distributed, it can be seen that any bypass componentscreate frequency dependent alterations in the power distribution systemimpedance. For frequencies below those where the distance is asubstantial fraction of the wavelength in the effective dielectricmedium, the distributed bypass and wiring networks can be modeled assimpler one-dimensional branches, similar to the model of Baudendistel.

The most troublesome resonance is the transition between the highestfrequency R-L-C branch and the lumped power/ground cavity capacitance.For most PCBs, a model of which is shown in FIG. 10 (where transmissionlines 19, bypass elements 20, and IC load 21 are modeled), power/groundcavity capacitance is very limited and set by:

C=Area/Height*ε₀*ε_(R)

where C is the capacitance in Farads, Area is the plane cavity surfacearea, Height is the plane cavity thickness, ε₀ is the permittivity offree space, and ε_(R) is the relative permittivity of the dielectricmaterial in the plane cavity.

Example capacitances per square inch and impedances for four squareinches, which would be typical of a board section occupied by a sizableIC, of a board at several frequencies using typical PCB dielectrics areshown in the following table:

Z in Ohms @ F in MHz, 4 inches square H ∈_(R) C/sq in 100 200 500 10000.040 4.0 22.5 pF  17.7 8.85 3.54 1.77 0.010 4.0 90.0 pF  4.42 2.21 0.880.44 0.004 4.0 225 pF 1.77 0.88 0.35 0.18 0.002 4.0 450 pF 0.88 0.440.18 0.09 0.001 4.0 900 pF 0.44 0.22 0.09 0.04

A cavity height of 0.040″ is typical for low cost four or six layerconstruction. Cavity heights of 0.004″ are typical for processing ofcomplex fiberglass reinforced PCBs.

Given a uniform or nearly uniform distribution throughout a network ofbypass capacitors exhibiting a fixed mounted inductance, the transitionfrequency between the bypass capacitor network and the power/groundcavity of the PCB depends on the following parameters:

1. L_(CAP) _(—) _(MOUNTED), the mounted inductance of each bypasscapacitor;

2. P, the areal density of bypass capacitors;

3. C_(PLN) _(—) _(SQ) _(—) _(IN), the capacitance per unit area of thepower/ground cavity;

4. F_(RES)=P^(0.5)/(2*πL_(CAP) _(—) MOUNTED^(0.5)*C_(PLN) _(—) _(SQ)_(—) _(IN) ^(0.5));

5. Z_(CHAR)≈L_(CAP) _(—) _(MOUNTED) ^(0.5)*P^(0.5)); and

6. Z_(RES)≈L_(CAP) _(—) _(MOUNTED)/R_(CAP) _(—) _(MOUNTED)*C_(PLN) _(—)_(SQ) _(—) _(IN));

where F_(RES) is the resonant frequency, Z_(cHAR) is the characteristicimpedance of the reactive network consisting of the mounted bypasscapacitors and the lumped representation of the power wiringcapacitance, and Z_(RES) is the peak impedance at the pole formed fromthe bypass capacitor network and the lumped power wiring capacitance.

Increasing the bypass capacitor density increases the resonant frequencyand decreases the characteristic impedance of the pole formed betweenthe bypass capacitor network and the power/ground cavity of the PCB.However, increasing the capacitor density also reduces resistance perunit area, which increases the impedance peak with respect to thecharacteristic impedance, i.e., the circuit Q factor is increased.

The prior art methods that have been used to limit Z_(RES), or theimpact of Z_(RES), include:

1. Increasing the gross density of the bypass capacitors with matchingseries resistance so as to limit the circuit Q factor, which isdescribed by Baudendistel, Yamamura et al., Novak '258, and Novak '622;or

2. Increasing the capacitance of the power plane cavity.

Each of these methods has serious drawbacks. In the first method, thenumber of components required can become large, particularly for thickprinted circuit assemblies where the distance from the mounting surfaceof the capacitors and the planes and associated mounted inductance loopcan be large.

The second method requires use of expensive and sometimes difficult tohandle thin and/or high permittivity dielectric materials. A subtle,potential disadvantage of the second method is that it reduces theresonant frequency between the bypass capacitors and power/groundcavity.

Lee et al. enumerates distributed element modeling of a powerdistribution system using a two dimensional grid of either discreteR-L-C-G element cells or meshed transmission lines. In a powerdistribution system model incorporating both Baudendistel and Lee etal., the aggregate bypass capacitor network aggregates to a single R-L-Cbranch for each value of capacitor used. The value for R is the parallelmounted ESR of all capacitors of the particular value forming thebranch. The value for L is similarly the parallel mounted capacitorinductance. Finally, C is the parallel capacitance of the capacitors inthe branch.

It can be seen from this model that in order for each damping element tobe effective at frequencies where L_(PLN) is significant, the inductanceof the damping element, L_(DAMP), must be small in relation to L_(PLN).Lee et al. shows that modal resonances occur at frequencies whereL_(PLN) is significant.

In the prior art, interposers and modules have been used as componentcarriers for mechanical, space, and modularity reasons. For example,Alexander et al. (U.S. Pat. No. 6,961,231) discloses an interposer foruse with an IC. However, Alexander et al. uses the interposer merely asa means of providing capacitance to supplant the power system. Alexanderet al. does not use the interposer to reduce power system impedance, todetune power system resonance, and to redistribute input/output (I/O) toreduce noise injection into the PCB power wiring network caused bydiscontinuous return paths. The decoupling of the Alexander et al.interposer simply provides some non-specific amount of capacitance. Theresonant impedance of two parallel branches is theoretically unaffectedby the capacitance of the lower frequency branch. Increasing thecapacitance of that branch does not help reduce the troublesomeresonance. Adding capacitance to the interposer is only beneficial inreducing resonance between the next lower frequency branch and theinterposer. What constitutes that next lower branch depends on both theinterposer design and the attached components, such as packaged IC,discrete capacitors, and/or unpackaged IC dice. As such, the additionalcapacitance disclosed by Alexander et al. may be of little or no benefitto power distribution impedance.

A final problem not recognized or addressed in the prior art is theloading effects of bypass devices and IC loads on the power distributionsystem. The prior art relies upon a presumption that the powerdistribution system impedance is low compared to the devices served. Asdevice performance increases in frequency and power, establishing such adistribution system becomes difficult and costly, if not impossible.

SUMMARY OF THE DISCLOSURE

To overcome the problems described above, the preferred embodiments ofpresent invention provide isolation of the reactive impedanceinterdependencies of multiple ICs connected to a common powerdistribution system, match impedance to IC loads, and effect lower powerdistribution impedances across wider frequency ranges than currentlyavailable.

The preferred embodiments of the present invention extend beyond Novak'258 and '774 by loading a cavity boundary with dissipative elementssuch that the impedance at the boundary remains substantively uniformwith the impedance well within the boundary. This contrasts with Novak'258 where dissipative elements are used to match the average unloadedcavity impedance and with Novak '774, which calculates cavity impedancebased on plane separation, dielectric permittivity, and cavity perimeterwithout considering the loading effects of the bypass capacitors andactive circuits.

The preferred embodiments of the present invention provide methods todamp resonance between a bypass capacitor network and a power/groundcavity of the PCB that:

1. Does not require excessive quantities of bypass/damping components;or

2. Does not require high plane cavity capacitance or in the alternativecan insure a Q of less than about 1.4 at the transition from the bypassnetwork to the plane cavity impedance cross-over.

The preferred embodiments of the present invention are capable ofachieving one or more of the following:

1. Isolating the reactive impedance interdependencies of multipleintegrated circuits connected to a common power distribution system;

2. Presenting a matched impedance to IC loads; and

3. Effecting lower power distribution impedances across wider frequencyranges than currently available.

Other features, elements, characteristics, steps and advantages of thepresent invention will become more apparent from the following detaileddescription of preferred embodiments of the present invention withreference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-11 illustrate prior art techniques.

FIG. 12 illustrates an interposer according to a preferred embodiment ofthe present invention.

FIG. 13 illustrates various inductance loops in a PCB.

FIG. 14 illustrates an interposer according to a preferred embodiment ofthe present invention.

FIG. 15 illustrates half wave resonators according to a preferredembodiment of the present invention.

FIG. 16 illustrates an interposer according to a preferred embodiment ofthe present invention.

FIG. 17A illustrates a known power distribution system.

FIG. 17B is a close-up sectional view of signal traces of the knownpower distribution system illustrated in FIG. 17A.

FIGS. 18A illustrates a power distribution system according to apreferred embodiment of the present invention.

FIG. 18B is a close-up sectional view of signal traces of the knownpower distribution system according to a preferred embodiment of thepresent invention illustrated in FIG. 18A.

FIG. 19A illustrates a power distribution system according to apreferred embodiment of the present invention.

FIG. 19B is a close-up sectional view of signal traces of the knownpower distribution system according to a preferred embodiment of thepresent invention illustrated in FIG. 19A.

FIG. 20A illustrates a known possible arrangement of z-axisinterconnects.

FIG. 20B illustrates a circuit diagram of the arrangement illustrated inFIG. 20A.

FIG. 20C illustrates possible z-axis interconnects according to apreferred embodiment of the present invention.

FIG. 20D illustrates a circuit diagram of the arrangement illustrated inFIG. 20C according to a preferred embodiment of the present invention.

FIGS. 21A and 21B are circuit diagrams of an arrangement of aninterposer according to a preferred embodiment of the present inventionillustrated, respectively, in FIGS. 21C and 21D.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Techniques Used inOptimizing the Power Distribution System

As shown in the power distribution system 100 of FIG. 12, the pairs ofpower and ground planes 111 of the PCB 110 can be paired together totake advantage of mutual inductance and interplane capacitance. Themutual inductance of the power and ground planes 111 of the PCB 110reduces overall the inductance of the power distribution path. Thereduction of inductance of the power distribution path increases thepower distribution bandwidth. The interplane capacitance of the powerand ground planes 111 of the PCB 110 provides a small amount of energystorage, but interacts with the other parallel inductances in the powerdistribution system 100. This is a critical parameter at highfrequencies.

Capacitors 112 on the PCB 110 provide for energy storage in the powerdistribution system 100. Capacitors 112, 122, and 132 can be mounted ona substrate, including the PCB 110, the interposer 120, and the ICpackage 130, or can be embedded in a substrate. Capacitors 112, 122, and132 can also be mounted on the top or the bottom of the PCB 110, theinterposer 120, or the IC package 130.

Capacitors 112, 122, and 132 inherently have some amount of inductanceand resistance, along with capacitance, associated with their designs.The inherent inductances and resistances of the mounted capacitors mustbe taken into account when optimizing power distribution. Capacitors112, 122, and 132 are generally mounted to substrates with metal padsand vias. Capacitors 112, 122, and 132 have inductance associated withthe method used for attachment to the substrate. This inductance reducesthe power distribution bandwidth and causes interactions with otherpower distribution elements, including other capacitors and planarcapacitance. These interactions must be accounted for in optimizing thepower distribution system 100. Capacitors can also be created usingplanar substrate structures (embedded capacitors (not shown)) for use inhigh frequency tuning.

Tuned planar metal structures within one or more of the substrates canbe used to tune the frequency response of the power distribution system.These structures can be used to extend power system bandwidth. Thesestructures include embedded capacitors, embedded inductors, embeddedtransmission lines, embedded resonators (quarter and half wave), andembedded resistors. Additional resistive elements can be added, eitheras embedded structures, material property controlled attach structures,or external discrete components, for the purpose of controlling thedampening properties (Q factor) of resonant structures.

Plane position can be optimized in the IC package 130, the interposer120, or the PCB 110. Preferably, the plane position is optimized acrossthe entire power distribution system 100. Plane size can also beoptimized in the IC package 130, the interposer 120, or the PCB 110. Thereduction of plane size is used to increase the parallel resonantfrequency (PRF) of the power distribution system.

The planar metal structures that are used for resonance tuning/detuningcan be located in the IC package 130, the interposer 120, or the PCB110. Internal metal structures (inductors, capacitors, transmissionlines, resonators) can be fabricated so as to perform electricalcompensation, i.e., form equivalent lumped network parasitics and/orquarter/half wave resonant structures designed as compensating elements,and automatically track the substrate material and fabrication process.Any structure used as a compensating element that is formed from aportion of another larger structure that also contains a third structurebeing compensated exhibits the same electrical property changes as thethird element in response to manufacturing variations, as well as theoperating environment. For example, a capacitor formed from one portionof a plane that is used as a compensating element to a resonant poleformed by a larger portion of the same plane and discrete componentswill proportionately track the capacitance of the larger plane section.

Resistors (not shown) can be used for termination, i.e., resistiveelements in any form can be used to match the impedance of atransmission structure and can be used for resonance Q factor reductiontechniques. Resistors can be disposed as discrete devices on the top orthe bottom of the IC package 130, the interposer 120, or the PCB 110 orcan be embedded in the IC package 130, the interposer 120, or the PCB110. Resistors can be formed as embedded substrate elements, utilizingstandard embedded resistors processes. Resistors can be formed usingother materials, such as controlled resistance attachment solders andepoxies. These materials can include epoxy adhesives that include acombination of conductive and/or semiconductive materials suspended in acolloid prior to curing. Exemplary materials include, but are notlimited to: copper, aluminum, silver, iron, tin, nickel, gold, carbon,silicon, combinations and alloys thereof.

As shown in FIG. 13, inductance loops can be optimized as discussedbelow. The inductance through a capacitor 200 can be optimized by deviceselection and pad attachment design or by location of the closer poweror ground plane 205 of the PCB 208 that the capacitor attaches to. Theinductance through capacitor vias 201 can be optimized by the design ofthe vias 204, by via separation, by the location of the further power orground plane 205, or by the use of additional vias. The inductancecaused by ground and power plane spreading 202 can be optimized by theseparation of plane 205 pairs or by the distance between the capacitor207 and the IC package 206. The inductance through IC attach 203 can beoptimized by the design of vias 204, by via separation, or by the use ofadditional vias.

Other techniques can also be used to optimize the power distributionsystem. The key is to obtain low impedance, including most often lowinductive reactance. Not only is it important to consider the compleximpedance magnitude as recognized in the prior art, but also to considerthe complex impedance phase because the proper management of the phasereduces and/or completely eliminates troublesome resonances. Anytechnique that can manage the phase or magnitude can be used with theoptimization methods discussed above.

Optimization Methods of the Power Distribution System

Optimization methods for the power distribution system include one ormore of gross impedance reduction, planar inductance reduction, anddelivered power inductance reduction.

Gross impedance reduction can be achieved by increasing the capacitancerelative to the inductance with discrete or internal planar capacitors,decreasing the mounted capacitor inductance, and/or by optimizedmounting solutions, which include through the measurement of theimpedance, through the electromagnetic field simulation of the powerdistribution system, or through the optimized positioning of thecomponents, and optimizing the power wiring inductance.

Planar inductance reduction can be achieved by reducing the separationbetween power/ground planes, (cavity height), and/or use of multipleplane sets in parallel.

Inductance between the bypass capacitors and the power wiring can beachieved by selection of the Z-axis plane location with respect to thecapacitor mounting locations. Additionally, the geometry and quantity ofthe Z axis interconnects between the power wiring structure, typicallyplanes, and any given capacitor and/or capacitor groups impacts theeffective inductance of such an interconnect.

Similarly, inductance between the power wiring and any given IC issubject to the distance between the power wiring plane(s) and the ICdie. As with the bypass capacitors, the geometry and quantity ofinterconnects between the power wiring structure and the die determinesthe total inductance. In both cases, because it is desirable to minimizeinductance materials with the lowest relative permeability, 1.0 isassumed. Non-ferrous metals such as copper, silver, and other suitablemetals have relative permeabilities of about 1.0. Interconnects includePCB vias, traces, polygon fills, and other suitable interconnects.

Optimization methods for the power distribution system can include oneor more of the following impedance reduction methods:

1. Pole/Zero Compensation Method;

2. Pole/Pole Compensation Method;

3. Pole/Multi-Zero Compensation Method;

4. Signal Harmonic Compensation Method; or

5. Quarter Wave Resonance Method.

1. Pole-Zero Optimization Method

In a power distribution system with multiple pole pairs, each pole pairresults from the parallel resonance between the inductance of a firstnetwork branch with the capacitance of a second network branch. A branchincludes one or more elements. Typically, the first network branchconsists of the equivalent transfer function of a voltage regulatormodule connected to the power system wiring as a first shunt branch.Additional shunt branches typically include a quantity of capacitors ofa single value in each branch also connected across the power wiringnetwork as shown, for example, in FIG. 1. Each branch N exhibits ahigher self-resonant frequency than the preceding branch N−1. In theidealized case, the characteristic impedance, defined by the ratio ofthe mounted inductance to the capacitance, of all branches is equal. Asdemonstrated by Baudendistal, with sufficient resistive impedance ineach branch, impedance variations of the power distribution system canbe suppressed.

Each branch results in a complex admittance (the inverse of impedance)that shunts the power wiring network. Most reactive interaction occursbetween branches in pairs determined by the self-resonant frequency ofeach branch. This can be expressed in a simplified view as theinductance of branch N−1 interacting with the capacitance of branch N,for example, branches C_(val1) and C_(val2) shown in FIG. 1. When theself-resonant frequencies of each branch are well separated, thisapproximate view affords a fairly accurate approximation. When branchSRFs are tightly spaced significant interaction occurs between morediverse branches.

Up to the first half-wave modal resonance, the power wiring networksexhibit self impedances very similar to bypass capacitors. From DC to afrequency defined by the structure geometry, the insulator effectivepermittivity (dielectric constant), and the location within the network,the power wiring network self-impedance decreases with increasingfrequency and the phase remains close to −90°. At the defined frequency,a zero singularity occurs. The minimum impedance is reached at the zeroas the phase quickly transitions from nearly −90° through 0°, and tonearly +90°, where it remains up to the first half wave modal resonanceassociated with an impedance peak. Locations near the center of thepower wiring network exhibit the highest frequency zero, while thoseclosest to the power wiring network edges exhibit the lowest frequencyzero. For a uniform square cavity, the center zero occurs at about:F_(ZERO)=2,400 MHz/(Width_(INCHES)*ε_(R) ^(0.5)), where Width_(INCHES)is the width in inches of the full side of the plane. Near the corners,the zero frequency occurs at about: F_(ZERO)=1600 MHz/(Inches*ε_(R)^(0.5)), where Inches is the length of a full side of the plane.

For an ε_(R) of 4.0 and even for a large 16″×16″ structure, thefrequency ranges from 50 MHz near the power wiring network corners to 75MHz near the center. This is generally higher than the self-resonantfrequency of the mounted bypass capacitors. For the most common types ofbypass capacitors and mounting arrangements, self-resonant frequenciesrarely exceed 50-60 MHz and are most often 20 MHz or lower. As aconsequence, bypass capacitor networks traditionally appear inductiveover a frequency range where the self-impedance of any given point inthe unloaded power wiring network still appears capacitive. The resultis a parallel resonant equivalent circuit that exhibits an impedancemaximum at the resonant frequency. This resonance can be suppressed byseveral methods, including the addition of resistance into the bypasscapacitor branches as taught by Baudendistal.

This optimization method includes the suppression and the outrightelimination of the resonant behavior by altering the net phasecharacteristics of the loaded power wiring structure. The optimalvariation is a practical balance that depends substantively on the zerofrequencies of the power wiring structure.

In this optimization method, the shunt network can be designed with aseries of branches each with its own zero such that the self impedanceof the composite network remains within 135° electrical of the powerwiring network self-impedance phase at any point in the power wiringnetwork. The shunt network can include one or more planar capacitorsformed into the same or additional substrates as the power wiringnetwork. This optimization method can include the steps of, amongothers:

1. Determine the maximum tolerable high frequency self impedance of thepower wiring network;

2. Determine from the physical size of the power wiring network requiredwhether the power wiring network must meet the stipulated impedance ator above the half wave mode represented by a structure with a nominalε_(R) for the preferred dielectric cavity material, typically 4.0;

3. Construct a surface map model of the power wiring network;

4. Map the equivalent parasitics of the mounted IC power inputs to themap constructed in step 3; and

5. Map the complex self impedance of the map constructed in steps 3 and4 to a resolution nominally not less than one cell per 0.25″.

In this optimization method, additional shunt network(s) is (are)arranged such that the phase response between the IC die and the powerdistribution system is controlled by a third shunt element. The thirdshunt network has a series resonant frequency at or near the parallelresonant frequency of the first and second components/networks, has a Qfactor of about 2 or less, and has a characteristic impedance of thereactive elements that is not more than about2.0×√(L_(first)/C_(second)), where L_(first) is the inductance of thefirst element or network and C_(second) is the capacitance of the secondelement or network.

When the parallel resonance between the inductance of the first networkwith the capacitance of the second network is not damped with a Q factorless than or equal to about 1.4, the parallel resonance so formed cancause adverse results, such as:

1. Location of a resonant peak within the power transfer bandwidthbetween a PCB or PCB like assembly and a component subassembly, such asa packaged IC; and

2. Location of a resonant peak within the higher signal energy spectraof an attached load, such as an IC.

The Q factor and the SRF of the third shunt network can be set by usingany of the techniques discussed above. The third shunt network can bearranged to be included in the PCB 110, in the interposer 120, or the ICpackage 130 as shown in FIG. 12. It is possible that the third shuntnetwork can be arranged to be included on more than one of the PCB 110,the interposer 120, and the IC package 130. As shown in FIG. 14, theinterposer 120′ can include top 123 a and bottom 123 b tiers on wings123, where the bottom tier 123 b elevates the top tier 123 a above thecomponents 113 such that the interposer 120′ can have a greater areacompared to the interposer 120 of FIG. 12 without an elevating bottomtier 123 b. The additional area of the top tier 123 a allows for theplacement of additional components, including capacitors 122, on theinterposer 120′.

The benefits of using an interposer 120, 120′ include one or more of thefollowing:

1. Intended for design retrofit;

2. Connects 1:1 from PCB to IC ball grid array (BGA);

3. Provides flat, wide bandwidth power to IC;

4. Suppresses IC

PCB resonances;

5. Filters noise between IC and PCB;

6. Low Q power distribution very forgiving to PCB design;

7. Application PCB need only meet maximum L and maximum Rspecifications;

8. Riser lifts interposer structure 0.050″ to clear existing SMTcomponents on PCB; and

9. Solves power delivery issues in existing designs.

If the third shunt network is included in the PCB 110, the capacitanceof the third shunt network can be set, for example, by dividing theplanes embedded in the PCB 110. The divided planes of the third shuntnetwork can form an island such that the remaining portion of the planescompletely surround the divided planes of the third shunt network, orthe divided planes of the third shunt network can include at least oneedge of the PCB 110 such that the remaining portion of the planes of thePCB 110 do not completely surround the divided planes of the third shuntnetwork.

The third shunt network can also include a resistive component that isformed from a planar structure formed in a PCB 110.

2. Pole-Pole Optimization Method

In this optimization method, the third shunt network is inserted inseries between the first network and the second network.

The third series network, when loaded by the first network, has aparallel resonant frequency at or near the parallel resonant frequencyof the first and second networks, has a Q factor of about 2 or less, andhas a characteristic impedance of the reactive elements of not more thanabout 2.0×√(L_(first)/C_(second)), where L_(first) is the inductance ofthe first element or network and C_(second) is the capacitance of thesecond element or network.

The third series network described can include a resistive componentformed from a planar structure formed in a printed circuit structure.The capacitive and inductive reactances of the third series network canbe formed by the combination of a discrete surface mount capacitor andprinted-circuit etch features. The surface mount capacitor can be of anX2Y® design, feedthrough capacitor, or transmission line capacitor suchas NEC® Proadlizer®.

3. Pole-Multi-Zero Optimization Method

A refinement of the pole-zero optimization method and the pole-poleoptimization method is when the individual resonant networks are formedfrom groups of networks, where at least one of the networks can becomposed of a plurality of capacitors where:

1. The capacitances within the at least one network can span a narrowrange using multiple successive E12 series values. For example, use of 1nF, 1.2 nF, and 1.5 nF components; and

2. Multiple mounting structures are optionally used that displace theeffective mounted inductance by small amounts, typically less than 20%.The mounting structure can include variations in via diameter, via tovia spacing, and geometry of via to component pad etch.

The resulting network has a greatly lowered Q factor compared with anetwork composed of a single discrete capacitor value, and in many casesobviates the need for a discrete resistance element in order to achievea low Q factor response.

4. Quarter/Half Wave Resonance Optimization Method

An additional optimization method includes providing a first series ofquarter-wave resonator stubs 302 that emanate from the powerdistribution vias 301 of each IC as shown in FIG. 15. The vias 301 canbe located in the PCB 110, the interposer 120, or the IC package 130.The frequencies of the first series of quarter-wave resonator stubs 302are selected to correspond to the half wave resonances of theuncompensated power distribution system. The impedances of the firstseries of quarter-wave resonator stubs 302 are selected in linearlyascending values with frequency to minimize the negative impact of thehalf-wave resonance modes that result from each the first series ofquarter-wave resonator stubs 302. A second series of quarter-waveresonator stubs (not shown) can also be provided to compensate thehalf-wave modes resulting from the first series of quarter-waveresonator stubs, resulting in an overall frequency response that has amuch flatter impedance than achievable with a like planar area and layercount. The second series of quarter-wave resonator stubs can be locatedin the same plane as the first series of quarter-wave resonator stubs orcan be located in a different plane. The second series of quarter-waveresonator stubs can be located in a different device from the firstseries of quarter-wave resonator stubs 302. For example, the firstseries of quarter-wave resonator stubs 302 can be located in the PCB110, and the second series of quarter-wave resonator stubs can belocated in the interposer 120 or 120′.

This optimization method is most applicable when the compensationstructure is in IC packages or interposers. However, this optimizationmethod can also be used when the compensation structure is in PCBs. Thindielectrics, with or without high dielectric constant materials, can beused with this optimization method because these materials exhibit muchlower inherent Q factors because of the higher ratio of the resistiveskin loss to the inductance.

In many commonly used geometries, an unattainable combination ofmaterial dielectric constant and thickness is required to reach a Qfactor of less than about 2 utilizing quarter wave resonators. Theresult is that the impedance of a plane cavity using existing materialsis limited to shunt impedances in the neighborhood of 60×10⁻³ ohms inthe 1 GHz to 8 GHz region, with substantial modulation. By simplyconnecting two like cavities together, these impedances can be droppedto the 30×10⁻³ Ohms range. This optimization method makes substantiallybetter use of available physical resources and can, with two cavities,drop the total impedance to between 10×10⁻³ and 20×10⁻³ Ohms over thissame frequency range.

5. Harmonic Suppression

Another optimization method minimizes the cost of power distributionelements by optimizing the transition frequency from the discrete PCBlevel bypass capacitors to either the capacitance within the IC or tothe planar bypass elements (power planes), by setting the transitionfrequency to a value from between about 1.8 times, but no more thanabout 2.2 times the non-return-to-zero (NRZ) bit frequency of thehighest frequency noise generating source of any substantial power.

The transition frequency is a function of the following parameters:

1. Areal density of the discrete bypass capacitors: P;

2. Mounted inductance of individual bypass capacitors: L_(MOUNT);

3. Dielectric constant of planar cavity insulator material: ε_(R)*ε₀,

4. Thickness of planar cavity insulator material: H;

5. Percentage perforation of planar cavities;

6. Spatial distribution of discrete bypass capacitors;

7. Spatial distribution of power, and power return connections to ICsconnected to the power cavity; and

8. Energy storage elements, discrete, or semiconductor die within ICsconnected to the power cavity.

This optimization method minimizes the integral of the product ofcombined IC/PCB/bypass network impedance and noise source energy. TheNRZ energy exhibits a frequency spectra with a “comb” shape where thepeaks decline on a linear slope from half the bit repetition rate to thehighest odd multiple of half the bit repetition rate withinapproximately 0.5 divided by the signal rise-time, beyond which signalenergy drops much more rapidly. Between the impedance peaks aresubstantial impedance nulls. This optimization method places a resonancewithin one of the nulls above the third harmonic of the highest possibledata rate, typically between the third and fifth harmonics at 1.8 to 2.2times the clock rate. This placement of the resonance guarantees thatfor an arbitrary data pattern, the ninth harmonic is the lowest bit rateharmonic that can align to the transition frequency. Values as low as1.65 can be used with the impairment that the seventh harmonic of a lowfrequency bit pattern excites 1.75-times the maximum bit rate.

Generally, the more capacitors of a given mounted inductance that areattached to a PCB, the higher the transition frequency where thereactance of the planar plate capacitance crosses the reactance of thecapacitor network mounted inductance. However, for a given capacitormounted inductance and ESR, whenever the transition Q factor issubstantially greater than 2, the addition of more capacitors fails toalter the theoretical peak impedance at the transition because, whilethe characteristic impedance of the composite network follows the platecapacitor impedance down, the Q factor goes up by an identical slope.One desirable characteristic of an increased Q factor is a narrowerpercentage bandwidth. This makes the network resonance easier to detune.An optimization technique consists of selecting a bypass capacitor arealdensity such that the resulting resonance between the bypass capacitornetwork combined with the shunt impedance of any other devices, such asICs, occurs at a frequency that can be practically damped with the useof one of the aforementioned compensation techniques.

The above described optimization methods can be used for a single IC ona PCB or multiple ICs on a PCB. The optimization methods can be usedseparately or in combination with one another. Typically, the pole-zerooptimization method will be used, either separately or in combinationwith the other optimization methods.

Interposer

An interposer 120, 120′ that can include discrete bypass capacitors 122can be placed between an IC package 130 and an application PCB 110. Theinterposer 120, 120′ may preferably include a series of metallic layerplanes 121, e.g., copper, laminated between organic dielectricmaterials. An IC package 130 can be mounted to the top of the interposer120, 120′ in a normal solder reflow or adhesive cure process. Any othersuitable method can also be used to mount the IC package 130. However,the interposer 120, 120′ outline is substantially larger than theattached IC package 130 to allow for attachment of discrete bypasscapacitors 122 and other discrete components as required by theapplication. The interposer 120, 120′ can include one or more powersupply functions implemented with linear or switch mode methods.

The interposer 120, 120′ typically attaches to the application PCB 110using normal solder reflow or conductive adhesive cure process. Othersuitable methods of attaching the interposer 120, 120′ can also be used.

The interposer power distribution cavities are typically each composedof thin, less than or equal to about 35 μm or about 1 mil, dielectriccavities. The thickness and the dielectric constant of each cavity isselected according to the needs of the IC package 130 for which theinterposer 120, 120′ is designed. Discrete bypass capacitors 122 aretypically attached to the upper surface of the interposer 120, 120′ (ICpackage 130 mounting side), but can also attach to the bottom surface ofthe interposer 120, 120′. The power distribution for a single power railcan consist of (1) a cavity over substantially the entire extent of theinterposer 120, 120′, (2) multiple such cavities, or (3) a subsection ofsuch a cavity, as determined by the power requirements of the die 133and the IC package 130 that the interposer 120, 120′ is designed tointerface.

The interposer 120, 120′ can include the use of resistive elements inany and/or all forms, including discrete surface mount components,planar resistors such as Omega, and/or vertical contact resistors formedfrom a cured epoxy/carbon and/or copper or silver matrix.

Resistive elements can occur in any combination of (1) in series betweenthe power cavity(s) and the application PCB attachment on the interposerbottom side, (2) in series with the discrete bypass capacitors 122mounted on the interposer 120, 120′, (3) in series with the cavitysubsections on the interposer 120, 120′, and (4) in series between theinterposer power cavity(s) and the IC package 130.

The interposer 120, 120′ can include one or more pole-zero cancellationnetworks to suppress the resonance between the discrete bypasscapacitors 122 and the power cavity(s) in the interposer 120, 120′. Theinterposer 120, 120′ can include one or more pole-zero cancellationnetworks to reject the propagation of energy that occurs at or nearresonances within the attached IC package 130 to and from theapplication PCB 110.

The interposer 120, 120′ can include one or more pole-zero cancellationnetworks to suppress the resonance between the attached IC package 130and the interposer power cavity(s) and the discrete bypass capacitors122.

The interposer 120, 120′ can include one or more pole-pole cancellationnetworks to suppress the resonance between the discrete bypasscapacitors 122 and the power cavity(s) in the interposer 120, 120′.

The interposer 120, 120′ can include one or more pole-pole cancellationnetworks to suppress the resonance between the interposer 120, 120′ andthe attached IC package 130.

The interposer 120, 120′ can be constructed such that the resonance on agiven voltage rail between the discrete bypass capacitors 122 and theinterposer power cavity(s) lies from about 1.8 times to about 2.2 timesthe clock frequency of the highest I/O frequency on a given power railof the attached IC package 130.

The interposer 120, 120′ can be constructed such that the resonance on agiven voltage rail between the composite interposer 120, 120′ andattached IC package 130 lies from about 1.8 times to about 2.2 times theclock frequency of the highest I/O frequency on a given power rail ofthe attached IC package 130.

The interposer 120, 120′ can include one or more quarter wave resonatingstructures, as shown in FIG. 15, to suppress the modal resonances of anygiven power cavity(s) in the interposer 120, 120′.

The interposer 120, 120′ can include one or more low pass filterstructures to limit the high frequency content of the IC I/O signals.

The interposer 120, 120′ can include one or more transient suppressiondevices to provide protection to one or more IC pins.

The interposer 120, 120′ can include one or more linear or switchingpower supply circuits to regulate power to the IC package 130. Theinterposer 120, 120′ can include a power cavity close to the top surfaceof the interposer 120, 120′ and matching power cavity near the bottom ofthe interposer 120, 120′ connected through a plurality of verticalinterconnects, typically vias, so as to minimize the inductance betweenthe bypass components attached to either side of the interposer 120,120′ and both the attached IC package 130 and PCB 110. The benefit ofsuch an arrangement is reduced power supply impedance presented to boththe IC die 133 of the IC package 130 and the application PCB 110. Thisreduced impedance in both directions serves to substantively reducetransmission path discontinuities that occur when a planar signal linein the PCB 110 references one or the other voltage nodes of therespective I/O power rail, while the vertical interconnects from the PCB110 through the interposer 120, 120′ and the IC package 130 referenceseither the other respective voltage node or a combination of the twovoltage nodes of the respective I/O voltage rail. This improves both I/Osignal fidelity, and reduces the noise, including EMI that wouldotherwise propagate through the application PCB I/O power cavity(s).

By way of the tight rail to rail coupling afforded by the thindielectric layers of the interposer 120, 120′, the interposer 120, 120′improves the return path into the IC package 130 (not shown in FIG. 21Cor 21D) regardless of the I/O voltage plane, v_(dd) or v_(ss),referenced by the application signal in the signal trace 114 on the PCB110, as shown in FIGS. 21A and 21C and in FIGS. 21B and 21D. Thispermits possible reduction of the number of plane layers required in theapplication PCB 110 and permits possible improvement in signalperformance that cannot be matched by any known PCB construction.

The interposer 120, 120′ can remap the connections from the IC package130 to the application PCB 110 to any or any combination of purposes:

-   -   Reduce crosstalk between I/O signals by more optimal arrangement        than the original IC; and    -   Simplify power interconnect on the application PCB.

The interposer 120, 120′ can include attachment interconnects to theapplication PCB 110 outside the perimeter of the IC package 130. Theseinterconnects can be used for any combination of purposes:

-   -   Reduce the number of application PCB layers needed to        “break-out” the signal connections from the composite interposer        120, 120′/IC package 130 to the PCB 110 versus the original IC        connection pattern;    -   Reduce crosstalk between I/O signals by more optimal arrangement        than the original IC package; and    -   Simplify power interconnect on the application PCB 110.

As shown in FIG. 16, the interposer 120′ can include wings 123, whichextend beyond the portion of the interposer 120′ having an array of ICpackage interconnects connected to the IC package 130, that providelocations for the bypass capacitors 122. The interposer 120′ can includeone or more wings. Because the bypass capacitors 122 are located on thewings 123, neither the bypass capacitors 122 nor their respectivevertical interconnects compete with the vertical IC packageinterconnects between the substrate of the interposer 120′ and the PCB110 (not shown in FIG. 16) or the horizontal interconnects between thevertical IC package interconnects and the IC package 130 or IC die 133(neither shown in FIG. 16). Location of the bypass capacitors 122 on thewings 123 also facilitates thermal isolation between the bypasscapacitors 122 and the IC die 133 heat removal infrastructure.Optionally, the wings 123 are formed to include a limited number ofpower and power return vertical interconnects 124 to join the substrateof the interposer 120′ with the PCB 110. As a result, the followingbenefits are realized:

-   -   1. On the higher level assembly (typically the application PCB        110), bypass capacitors 122, and their associated vertical        interconnect are not required to be close to the substrate.        Instead, the low density power interconnects 124 are readily        traversed by signal traces 114 while maintaining generous        overlap of signal traces 114 by the associated reflection plane.        This is seen by comparing FIGS. 17 and 18. Prior Art FIG. 17        shows a conventional IC package 401 connected to a PCB 400.        Bypass capacitors 402 are attached to both surfaces of the PCB        400. The bypass capacitor interconnects 404 perforate the PCB        400. Signal traces 403 on reflection plane 405 must be routed        around both the bypass capacitor interconnects 404 and the        signal interconnects 406. FIG. 18 shows a subassembly 411, which        can be an interposer or an IC package according to one of the        preferred embodiments of the present invention, connected to a        PCB 410. Bypass capacitors 412 are attached to subassembly 411.        The bypass capacitor interconnects do not perforate the PCB 410        because they are located on the subassembly 411. Signal traces        413 that reference reflection plane 414 must be routed around        only the signal interconnects 416.    -   2. On the interposer 120′, the bypass capacitors 122 join to        voltage nodes through planar interconnects. Vertical signal        interconnect 125 does not substantively compete with the bypass        capacitor locations or interconnects.    -   3. By virtue of the thin interconnect structures between the        bypass capacitors 122 and the IC package 130/die 133 and of the        uninterrupted planar region on which the capacitors are mounted,        the IC package 130/die 133 to bypass capacitor 122 inductance is        minimized. Use of a thin dielectric within the limited extents        of the package reduces cost compared to use on the entire higher        level assembly, typically PCB 110.    -   4. 4. By virtue of the uninterrupted planar region on which the        bypass capacitors 122 are mounted, bypass capacitor 122 to        bypass capacitor 122 inductance can be minimized, thus reducing        the Q factor and the effects of parallel resonance between the        bypass capacitors 122 of different values.    -   5. When additional limited vertical power interconnects are used        between the substrate of the interposer 120, 120′ and the PCB        110, the lower density of the interconnects is much less        restrictive to signal routing than a fully populated        interconnect grid. As such, more signal traces 114 per planar        routing layer can be used in the PCB 110, as seen in FIG. 19.        FIG. 19 shows a subassembly 421, which can be an interposer or        an IC package according to one of the preferred embodiments of        the present invention, connected to a PCB 420. Bypass capacitors        422 are attached to subassembly 421. The bypass capacitor        interconnects do not perforate the PCB 420 because they are        located on the subassembly 421. Because the power interconnects        427 are located at the periphery of the subassembly 421, the        power interconnects 427 can be made less dense. Signal traces        423 on reflection plane 425 must be routed around both the power        interconnects 427 and the signal interconnects 426. However,        because the power interconnects 427 are less dense, the routing        of the signal traces 423 is easier.    -   For example, in a typical known package under common        manufacturing rules, vertical interconnects consist of 10 mil        drill holes, with 20 mil diameter capture pads and 28 mil        clearance diameters (anti-pads) on unconnected layers. A fully        populated signal grid utilizing 39.4 mil (1 mm) spacing nets        39.4 mil minus 28 mils=11.4 mils between anti-pad tangents.        Typically, only one signal on a 4 mil trace with 4 mil space        (typically 50 Ohm over 4 mil dielectric) can fit within the 11.4        mils. A second trace would require at a minimum: 4 mil trace, 4        mil space, second 4 mil trace, for 12 mils total, slightly        violating the anti-pads, and risking an electrical short.        Further, the anti-pad raises the trace impedance. The wings 123        of the interposer 120′ can be populated at a lower density, such        as about 78.7 mil (2 mm) pitch. Under the same manufacturing        rules stated above, the available routing area is about 78.7        mils minus about 28 mils=about 50.7 mils. Within the about 50.7        mils, six traces can be routed, equivalent to three traces for        each of the two columns. Additionally all six traces run over        solid plane and so do not suffer significant impedance        modulation as a result of traversing the additional vertical        power interconnect.    -   6. When additional vertical power interconnects are used at the        periphery of the interposer 120, 120′, the larger effective        working radius of the interconnect substantially improves the        inductance of the vertical interconnect between the interposer        120, 120′ and the PCB 110 reduces the inductance between the        interposer 120, 120′ and the PCB 110 improving the noise        filtering performance of the capacitors 122 included on the        interposer 120, 120′ with respect to the PCB 110.    -   7. When vertical power interconnects are restricted to the        periphery of the IC package 130 as seen in comparing FIGS. 20A        and 20B, the small inductance of the in-package power cavities        can be manipulated to enhance high frequency noise rejection        between the IC package 130/die 133 and the PCB 110. FIG. 20A        shows an array of interconnects that include v_(ss) 501 and        v_(dd) 502 power interconnects and signal interconnects 503. The        distance between the v_(ss) power interconnect 501 and the        v_(dd) power interconnect 502 is approximately 1.4 times the        pitch between adjacent interconnects. Signal interconnects        couple 70% with the closest V_(dd) 502/v_(ss) 501 power        interconnect and 30% with the closest v_(ss) 501/v_(dd) 502        power interconnect. As a result of this arrangement of        interconnects and as shown in the circuit diagram of FIG. 20B,        70% or 30% of the energy remains referenced to v_(ss) along path        A and 30% or 70% of the energy is diverted through the power        network wiring. FIG. 20C also shows an array of interconnects        that include v_(ss) 501 and v_(dd) 502 power interconnects and        signal interconnects 503. However, the signal interconnects 503        are arranged in array with a plurality of v_(ss) power        interconnects 502 interspersed in the array of signal        interconnects 503, and the v_(ss) 501 and V_(dd) 502 power        interconnects are arranged outside of the array of signal        interconnects 503. The distance between adjacent v_(ss) power        interconnects 501 and v_(dd) power interconnects arranged        outside of the array of signal interconnects 503 is        approximately the pitch between adjacent interconnects. Signal        interconnects 503 couple 70% with the closest v_(ss) power        interconnect 501 and 30% with the next closest v_(ss) power        interconnect 501. As a result of this arrangement of        interconnects and as shown in the circuit diagram of FIG. 20D,        virtually 100% of the energy remains referenced to v_(s), along        path C and 0% of the energy is diverted through the power        network wiring.    -   8. When the vertical power interconnects are restricted to the        periphery of the IC package 130 as seen in comparing FIGS. 20A        and 20B with FIGS. 20C and 20D, all vertical signal returns can        reference a single reflection reference, typically signal        common. Under these conditions, the impedance, allowable        inductance, and therefore number of power interconnects between        the interposer 120, 120′ and the PCB 110 is determined by power        delivery and not signal cross-talk/power bounce requirements.

IC Package

As shown in FIGS. 12 and 14, an IC package 130 can include discretebypass capacitors 132 placed on the periphery of a packaged integratedcircuit, where the IC package 130 has been extended beyond theboundaries normally required by its signal and power delivery pins. TheIC package 130 is typically composed of a series of metallic planes 131,e.g. copper, laminated between organic dielectric materials, as part ofa standard IC package process. An IC die 133 can be mounted to the topof the IC package 130 in a normal solder reflow or adhesive cureprocess. The IC die 133 can be mounted to the IC package 130 by anysuitable method. The IC package 130 outline is substantially larger thanwhat would normally be required by the IC die 133 to allow forattachment of additional bypass capacitors 132 and other discretecomponents (not shown) as required by the application. The IC package130 can include one or more switch mode power supply functions.

The IC package 130 can attach to an interposer 120, 120′ as shown inFIGS. 12 and 14 or can be directly attached to the application PCB 110using any suitable method, including using normal solder reflow,conductive adhesive cure process, pins, or land grid array structures,sockets, or other interposing structures.

The IC package power distribution cavities are typically each composedof thin, less than or equal to about 35 μm or about 1 mil, dielectriccavities. The thickness and the dielectric constant of each cavity isselected according to the needs of the IC for which the IC package 130is designed. Bypass capacitors 132 can be attached to the upper surfaceof the IC package 130 or can be embedded within the IC package 130. Thepower distribution for a single power rail can include (1) a cavity oversubstantially the entire extent of the IC package, (2) multiple suchcavities, or (3) a subsection of such a cavity, as determined by thepower requirements of the IC die 133 and the IC package 130.

The IC package 130 can include the use of resistive elements in anyand/or all forms, including discrete surface mount components, planarresistors such as Omega, and/or vertical contact resistors formed from acured epoxy/carbon and/or copper or silver matrix.

Resistive elements can occur in any combination of (1) in series betweenthe power cavity(s) and the application PCB 110, (2) in series with thediscrete bypass capacitors 132 mounted on the IC package 130, (3) inseries with the cavity subsections on the IC package 130, and (4) inseries between the package power cavity(s) and the IC package 130.

The IC package 130 can include one or more pole-zero cancellationnetworks to suppress the resonance between the discrete capacitors andthe power cavity(s) in the IC package 130. The IC package 130 caninclude one or more pole-zero cancellation networks to reject thepropagation of energy that occurs at or near resonances to and from theapplication PCB 110.

The IC package 130 can include one or more pole-zero cancellationnetworks to suppress the resonance between the attached die 133 and theIC package power cavity(s) and the bypass capacitors 132.

The IC package 130 can include one or more pole-pole cancellationnetworks to suppress the resonance between the discrete bypasscapacitors 132 and the power cavity(s) in the IC package 130.

The IC package 130 can include one or more pole-pole cancellationnetworks to suppress the resonance between the IC package 130 and theattached IC die 133.

The IC package 130 can be constructed such that the resonance on a givenvoltage rail between the discrete bypass capacitors 132 and the packagepower cavity(s) lies from about 1.8 times to about 2.2 times the clockfrequency of the highest I/O frequency on a given power rail of theattached IC die 133.

The IC package 130 can be constructed such that the resonance on a givenvoltage rail between the composite IC package 130 and the attached ICdie 133 lies from about 1.8 times to about 2.2 times the clock frequencyof the highest I/O frequency on a given power rail of the attached ICpackage 130.

The IC package 130 can include one or more quarter wave resonatingstructures to suppress the modal resonances of any given power cavity(s)in the IC package 130.

The IC package 130 can include one or more low pass filter structures tolimit the high frequency content of the IC I/O signals passing to andfrom the power wiring of the application PCB 110.

The IC package 130 can include one or more transient suppression devicesto provide protection to one or more IC pins.

The IC package 130 can include one or more linear or switching powersupply circuits to regulate power to the IC package 130. The IC package130 can include a power cavity close to the top surface of the ICpackage 130 and a matching power cavity near the bottom of the ICpackage 130 connected through a plurality of vertical interconnects,typically vias, to minimize the inductance between the bypass componentsattached to the IC package 130 and the PCB 110. The benefit of such anarrangement is reduced power supply impedance presented to both the ICdie 133 and the application PCB 110. This reduced impedance in bothdirections serves to substantively reduce transmission pathdiscontinuities that occur when a planar signal line in the PCB 110references one or the other voltage nodes of the respective I/O powerrail, while the vertical interconnects from the PCB 110 through the ICpackage 130 references either the other respective voltage node or acombination of the two voltage nodes of the respective I/O voltage rail.In turn, this improves both I/O signal fidelity, and reduces the noise,including EMI that would otherwise propagate through the application PCBI/O power cavity(s).

By way of the tight rail to rail coupling afforded by the thindielectric layers, the IC package 130 improves the return path into theIC die 133 regardless of the I/O voltage plane referenced by theapplication signal. This permits possible reduction of the number ofplane layers required in the application PCB 110.

The IC package 130 can remap the usual connections from the IC die 133to the application PCB 110 to any or any combination of purposes:

Reduce crosstalk between I/O signals by more optimal arrangement thanthe known IC die; and

Simplify power interconnect on the application PCB 110.

The IC package 130 can include attachment interconnects to theapplication PCB 110 outside the known perimeter of the IC package. Theseinterconnects can be used for any combination of purposes:

Reduce the number of application PCB layers needed to “break-out” thesignal connections from the IC package 130 to the PCB 110 versus theknown IC package connection pattern;

Reduce crosstalk between I/O signals by more optimal arrangement thanthe known IC package; and

Simplify power interconnect on the application PCB 110.

Applicants hereby incorporate by reference the subject matter disclosedin U.S. patent application Ser. Nos. 60/804,089; 60/887,148; and60/887,149.

It should be understood that the foregoing description is onlyillustrative of the present invention. Various alternatives andmodifications can be devised by those skilled in the art withoutdeparting from the present invention. Accordingly, the present inventionis intended to embrace all such alternatives, modifications, andvariances that fall within the scope of the appended claims.

1. An interposer comprising: a substrate having first and secondsurfaces; and a shunt network; wherein the first surface is arranged tobe attachable to a circuit board; the second surface is arranged to beconnectable to an integrated circuit package; and the shunt network hasa series resonant frequency at or near a parallel resonant frequency ofa first component having an inductance L_(first) and of a secondcomponent having a capacitance C_(second) of a power wiring network towhich the interposer will be connected.
 2. An interposer according toclaim 1, wherein the substrate includes at least one wing.
 3. Aninterposer according to claim 1, wherein the shunt network has a Qfactor of about 2 or less.
 4. An interposer according to claim 1,wherein the shunt network has a Q factor of about 1.4 or less.
 5. Aninterposer according to claim 1, wherein reactive elements of the shuntnetwork have a characteristic impedance more than2.0×√(L_(first)/C_(second)).
 6. An interposer according to claim 1,wherein the shunt network is arranged to suppress or eliminate resonantbehavior of a power wiring network by altering a net phasecharacteristics of the power wiring network when the shunt network isconnected to the power wiring network.
 7. An interposer according toclaim 1, wherein the shunt network includes a plurality of branches;each of the plurality of branches has its own zero such that the selfimpedance of the shunt network remains within 135° electrical of a powerwiring network self-impedance phase at any point in the power wiringnetwork when the shunt network is connected to the power wiring network.8. An interposer according to claim 1, wherein the shunt network isarranged to be insertable in series between the first component and thesecond component.
 9. An interposer according to claim 1, wherein theshunt network, when loaded by the first component, has a parallelresonant frequency at or near a parallel resonant frequency of the firstcomponent and the second component.
 10. An interposer according to claim1, wherein the shunt network includes a group of networks; and at leastone of the group of networks is composed of a plurality of capacitors.11. An interposer according to claim 10, wherein capacitances of theplurality of capacitors span a narrow range using multiple successiveE12 series values.
 12. An interposer comprising: a substrate havingfirst and second surfaces; a via disposed in the substrate; and a firstseries of quarter-wave resonator stubs connected to the via; wherein thefirst surface is arranged to be connectable to a circuit board; thesecond surface is arranged to be connectable to an integrated circuitpackage; and frequencies of the first series of quarter-wave resonatorstubs correspond to half wave resonances of a power wiring network whenthe power wiring network is not compensated.
 13. An interposer accordingto claim 12, wherein impedances of the first series of quarter-waveresonator stubs linearly ascend in values with frequency to minimize thenegative impact of half-wave resonance modes that result from each ofthe first series of quarter-wave resonator stubs.
 14. An interposeraccording to claim 12, further comprising a second series ofquarter-wave resonator stubs arranged to compensate half-wave resonancesresulting from the first series of quarter-wave resonator stubs.